ISD-200 Datasheet, PDF (49/64 Pages) List of Unclassifed Manufacturers – USB Mass Storage Class Bulk-Only Specification Compliant

ISD-200 ASIC Datasheet
USB Transceiver Timing Characteristics
The USS-725 USB transceiver complies with the timing and electrical requirements of the Universal Serial
Bus Specification version 1.0.
ATA/ATAPI Port Timing Characteristics
All input signals on the ATA/ATAPI port are considered to be asynchronous, and are synchronized to the
chip’s internal system clock. All output signals are clocked using the chip’s internal system clock, for
which there is no external reference. Thus, the output signals should be considered asynchronous.
PIO mode 0 (750 ns cycle time) shall be used during power on reset (POR) and for non-data register
accesses. Following POR, the PIO mode used for data register accesses is specified in the ISD-200
configuration bytes.
Clock
Frequency
Duty Cycle
external crystal
12 MHz ± 0.25%
n/a
Note: Clock signal frequency is measured at V_DD18/2 point. Rise and fall times should be 2 ns or less.
Table 19 – Clock Requirements
Reset
The ISD-200 requires an off-chip power-on reset circuit. The supply voltage should be stable for a
minimum of 1 ms prior to the release of nRESET.
In-System Design Confidential
47