ISD-200 Datasheet, PDF (15/64 Pages) List of Unclassifed Manufacturers – USB Mass Storage Class Bulk-Only Specification Compliant

ISD-200 ASIC Datasheet
commands by returning the defaults contained in the internal on-board ROM (See ATA/ATAPI Interface,
Vendor-Specific ATA Commands, Identify).
An example of vendor-specific Identify (FBh) data formatting is shown in Appendix A.
ISD-200 Configuration/USB Descriptor Data Formatting
Data formatting for all ISD-200 configuration data and USB descriptor data is identical for Internal ROM,
Serial ROM, and vendor-specific Identify (FBh) data. The following sections show how the ISD-200
configuration data is mapped into address space. The USB Interface section contains formatting of USB
descriptor data (See Tables 7-11).
ISD-200 Configuration Data
The ISD-200 Configuration Data is located in addresses 0 to 9 of the Descriptor/Configuration data
contents. These bytes are read at power up and determine certain parameters and operational modes used
by the ISD-200. Power-on reset default values are specified in bold.
Formatting is identical for the internal ROM, serial ROM, and vendor-specific Identify (FBh) data. See
Appendix A. The ISD-200 Configuration Bytes get loaded into internal registers, regardless of the original
data source.
Address
Field Name
Description
0x00
0x01
0x02
0x03
0x04
Data Signature (LSB)
Data Signature (MSB)
Event Notification
DPLL Parameters
ATA Initialization
Timeout
This field specifies the least significant byte of the Serial ROM/FBh
signature.
This register does not exist in HW (no POR values)
This field specifies the most significant byte of the Serial ROM/FBh
signature.
This register does not exist in HW (no POR values)
This field specifies the ATA event notification command. Setting this field to
0x00 disables this feature.
POR configuration default of 0x00
This field denotes the parameters used by the internal DPLL. The original
clock source is 12 MHz.
5 bits M (7:3), 2 bits N (2:1), 1 bit Enable (0). When enabled, multiply the
original clock source by M, divided by N
M:
00000 => M=1
00001 => M=1
00010 => M=2
00011 => M=3
….
11111 => M=31
N:
00 => N=1
01 => N=3
10 => N=2
11 => N=4
Enable: 0 => CLK_N disabled
1 => CLK_N enabled
POR configuration default of 0x00
This field specifies the time in multiples of 128 ms (0x19 = 3.2s) before the
ISD-200 stops polling the Alternate Status device register for reset complete
and restarts the reset process.
NOTE: The ROM contents ATA Initialization Timeout value must be large
enough to accommodate I_MODE operation during the first device
initialization sequence (before FBh configuration data load)
POR configuration default of 0x02
On-board
Defaults
0x52
0x48
0x00
0x00
0x19
In-System Design Confidential
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