ISD-200 Datasheet, PDF (33/64 Pages) List of Unclassifed Manufacturers – USB Mass Storage Class Bulk-Only Specification Compliant

ISD-200 ASIC Datasheet
ATA Command Block
ATA commands for the ISD-200 shall be supported by command encoding in the command block portion
of the MSC Command Block Wrapper (CBW). Refer to the USB Mass Storage Class (MSC) Bulk Only
Transport Specification for information on CBW formatting.
The ATA Command Block (ATACB) provides a means of passing ATA commands and ATA register
accesses for execution. The ATACB resides in the CBWCB portion of the CBW. The ATACB shall be
distinguished from other command blocks by the first two bytes of the command block matching the
wATACBSignature. Only command blocks that have a valid wATACBSignature shall be interpreted as
ATA Command Blocks. All other fields of the CBW and restrictions on the CBWCB shall remain as
defined in the USB Mass Storage Class Bulk Only Transport Specification. The ATACB shall be 16 bytes
in length. The following table and text defines the fields of the ATACB.
Byte
7
6
5
4
3
2
1
0
0-1
wATACBSignature
2
Reserved (0)
bmATACBActionSelect
3
bmATACBRegisterSelect
4
bATACBTransferBlockCount
5-12
bATACBTaskFileWriteData
13-15
Reserved (0)
Table 12 – ATA Command Block Formatting
Field Descriptions
wATACBSignature –
This signature indicates the CBWCB contains an ATACB. The signature field shall contain the
value 2424h to indicate an ATACB. Devices capable of accepting only ATA Command Blocks
shall return a command failed status if the wATACBSignature is not correct.
bmATACBActionSelect –
The bit fields of this register shall control the execution of the ATACB. Refer to the ATACB
Command Flow diagram in section 4 of this document for further clarification . The bitmap of the
bmATACBActionSelect shall be defined as follows:
Bits 7-6
Reserved - The host shall set these bits to zero.
Bit 5
DEVOverride – Use the DEV value specified in the ATACB.
0 = The DEV bit value will be determined from ISD200 Configuration data
(byte 5 bit 5)
1= Then DEV bit value will be determined from the ATACB(0xB bit 5).
Bits 4-3
DPErrorOverride(1:0) - Device and Phase Error Override. These bits shall not
be set in conjunction with bmATACBActionSelect TaskFileRead. The order of
precedence for error override shall be dependant on the amount of data left to
transfer when the error is detected, as depicted in the ATACB Command Flow
diagram.
00 = Data accesses are halted if a device or phase error is detected.
01 = Phase error conditions are not used to qualify the occurrence of data
accesses.
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