AB-2061G-33 Datasheet, PDF (4/32 Pages) List of Unclassifed Manufacturers – 33Mhz PCI to Local Bus Interface

Introduction
The AB-2061 device described in this document is intended to support a subset of
the PCI bus specification. However this does not preclude the use of this device
on standard PCI buses, as the electrical specifications are the same and the minimum
feature set is supported.
The device contains a number of shared registers for interprocessor communication
and mechanisms for generating interrupts to the PCI and local buses.
The device supports the transfer of blocks in a way which reduces load on the
local processor and also makes efficient use of the PCI bus by maintaining sensible
size bursts and reducing the number of single data phase transactions to a minimum.
In order to decouple the relative speed differences between the two buses, the
device incorporates a pair of FIFOs - First In First Out memory buffers, one for
each direction. Each FIFO can hold four 32-bit words.
There is no direct access to the local memory space provided by this device, and
the PCI side cannot set up DMA transfers which are solely under the control of the
local processor.
Communication between buses is via the 32 byte shared register block or the
mailbox registers.
AB-2061-33 has a 3.3v PCI bus interface which will operate at a maximum frequency
of 33MHz. The local processor bus can be run at either 3.3 or 5v depending upon
the power supply.
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