AB-2061G-33 Datasheet, PDF (10/32 Pages) List of Unclassifed Manufacturers – 33Mhz PCI to Local Bus Interface

On Chip Resources
Configuration Registers
The PCI specification requires a minimum set of configuration registers, taking up
some 64 bytes. These registers are accessible from the PCI bus via configuration
cycles, though not all are writable. The local processor also requires access to the
configuration registers in order to set them up with the correct values.
These registers are specified fully in the PCI Rev 2.1 Documentation.
Shared Register Block
The chip contains a block of registers 32 bytes in length. These are accessible via
PCI from the address held in the configuration register, Base Address 0 via normal
read/write cycles. Again the local processor also has access to these registers.
One of these holds the offset register which contains pointers to various on-chip
resources.
DMA Control
The DMA controller transfers data in both directions between the card local memory
and the peripheral memory, although only the local processor will need to co-
ordinate the transfers and be able to see the DMA control registers. Using DMA
in this manner makes it easier to transfer data on the PCI bus in bursts, and hence
decrease the amount of bus bandwidth taken up by the card. This could be
important for certain types of device which may not work if the PCI bus is heavily
loaded. A size of 16 bytes (4 long words) is ideal. Due to the potential difference
in clock speeds and bandwidths between the local PCI buses, FIFOs are necessary
to allow this. The controller allows one transfer of non-longword aligned blocks
by the use of the DMA_MASK register.
Mailbox Registers
There are two mailbox registers for interprocessor communications which generate
interrupts to the relevant processor when read from or written to. These interrupts
are individually maskable.
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