AB-2061G-33 Datasheet, PDF (12/32 Pages) List of Unclassifed Manufacturers – 33Mhz PCI to Local Bus Interface

RESOURCE_CONTROL Register
Bit Name
Function
0 DMA1_ENABLE
When set to 1 DMA channel #1 will start.
Writing a 0 will stop and reset the channel.
1 DMA1_PAUSE
Writing a 1 will cause DMA on channel
#1 to pause until a 0 is written when it will
recommence.
2 DMA2_ENABLE
When set to 1 DMA channel #2 will start
Writing a 0 will stop and reset the
channel.
3 DMA2_PAUSE
Writing a 1 will cause DMA on channel
#2 to pause until a 0 is written when it
will recommence.
4 FIFO2-FLUSH
Setting this bit to a 1 will allow the PCI
bus controller to perform bursts of less
than four long words. Used to flush last
bytes from the FIFO.
5 PROTECT_REGISTERS When set to 1 some registers in the shared
register block are write protected.
6 LOCK_REGISTERS
When 1 all PCI bus accesses to the shared
register block will be terminated with
RETRY. Set to 0 after reset.
7 CONFIG_ENABLE
When 0 all PCI configuration cycles will
be terminated with RETRY. Writing 1
will allow configuration cycles to proceed
normally. Set to 0 after a reset.
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