AB-2061G-33 Datasheet, PDF (29/32 Pages) List of Unclassifed Manufacturers – 33Mhz PCI to Local Bus Interface

3 or less longwords are left, the FIFO2_FLUSH bit must be set. This bit allows
DMA2 to initiate a burst with any quantity of data in FIFO2. Do not forget to reset
this bit after completion of the block transfer as it can dramatically reduce the
transfer speed and bus efficiency of AB2061.
NEVER attempt to reset the CONFIG_ENABLE bit in the RESOURCE_CONTROL
register when any DMA is running. Doing so causes AB2061 to enter a factory
test mode and will cause unpredictable PCI memory space corruption.
Reading and Writing Data
DMA data is read from and written to the FIFO_DATA register. This is either a 8
or 16 bit port depending on the data bus width. In 8 bit mode four sucessive reads
will retrieve one full 32 bit word from FIFO1 and 4 writes will place one 32 bit word
into FIFO2. The order that the bytes are written to and retrieved from the fifos is
determined by the ENDIAN bit in the RESOURCE_CONFIG register. In 16 bit
mode FIFO_DATA must be read and written as a 16 bit wide port, two reads/writes
are required per 32 bit word.
As an example, assume the top word of FIFO1 contains the value 00C0FFEEh.
In 8 bit mode with ENDIAN=0 four reads of FIFO_DATA return EE, FF, C0, 00
ENDIAN=1 four reads of FIFO_DATA return 00, C0, FF, EE
In 16 bit mode with ENDIAN=0 two reads of FIFO_DATA return FFEE, 00C0
ENDIAN=1 two reads of FIFO_DATA return 00C0, FFEE
Writing data to FIFO2 follows the same ordering convention.
The internal 'byte/word pointers' for this function are reset when a '0' is written to
the associated channel's DMA_ENABLE bit.
Local bus DMAC signals
AB2061 has a DMA request pin for each channel, this allows a simple twochannel
DMAC on the local bus to read and write the fifos without CPU intervention.
DMARREQ - Active low and asserted when FIFO1 contains data
DMAWREQ - Active low and asserted when FIFO2 has space for data
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