AB-2061G-33 Datasheet, PDF (16/32 Pages) List of Unclassifed Manufacturers – 33Mhz PCI to Local Bus Interface

DMA Control Registers
These can only be accessed by the local processor through an indirect method.
Local
Indirect
Addr.
18(3-0)
19(1,0)
19(3,2)
1A(3-0)
1B(1,0)
1B(1,0)
24(0)
24(1)
Name
DMA1_SOURCE_BASE
DMA1_LENGTH
DMA1_DEST_BASE
DMA2_DEST_BASE
DMA2_LENGTH
DMA2_SOURCE_BASE
DMA_MASK
RESOURCE_CONF
Width Function
3 2 Base address of DMA transfers from PCI > Local
1 6 Length in long words of PCI > Local DMA
1 6 NOT IMPLEMENTED
3 2 Base address of DMA transfers from Local > PCI
1 6 Length in long words of Local > PCI DMA
1 6 NOT IMPLEMENTED
8 Byte masks for first and last word in DMA
transfers
8 Bit 0 = local FIFO endian mode (see section on
DMA controller units)
Interrupt Control Registers
PCI
Address
30
34
38
Local
Indirect
Address
1C(3-0)
1D(3-0)
1E(3-0)
Name
Width Function
INTERRUPT_SET 32
INTERRUPT_CLEAR 3 2
INTERRUPT_STATUS 3 2
Written to by PCI to assert LINT
Written by local to assert PCI #INTA.
Written to by the PCI to clear PCI
INTA#. Written by local processor
to clear LINT.
Non zero to PCI when card is
asserting INTA#. Non zero to Local
when card is asserting Local INT.
The values written to INTERRUPT_SET and INTERRUPT_CLEAR are irrelevant.
Mailbox Registers
These registers are located in the memory space of PCI, addresses given are offsets
from the base address assigned to the chip.
Local access is through the indirect addressing, using the REGISTER_ADDRESS
and REGISTER_DATA0..3 ports.
PCI Addr. Indirect N a m e
Local
Addr.
Width Default
Value
40h
20h(3-0) Printer Control Register (PCR)
44h
21h(3-0) Printer Status Register (PSR)
48h
22h(3-0) Device Control Register (DCR)
4Ch
23h(3-0) Device Status Register (DSR)
70h
2Ch(3-0) Printer Handshake Register (PHR)
74h
2Dh(3-0) Device Handshake Register (DHR)
32
00000000h
32
00000000h
32
00000000h
32
00000000h
32
00000000h
32
00000000h
- 16 - rev 1.2