AB-2061G-33 Datasheet, PDF (28/32 Pages) List of Unclassifed Manufacturers – 33Mhz PCI to Local Bus Interface

DMA Status
The RESOURCE_STATUS register contains bits that allow the local processor to
monitor the progress or otherwise of ongoing DMA transfers.
DMA1_COMPLETE The last word of data has been placed in FIFO1 by DMA
channel 1. This DOES NOT however indicate that the data
is in local memory yet. (See FIFO1_EMPTY)
DMA2_COMPLETE DMA Channel2 has moved the last word from FIFO2 into
the PCI memory space.
FIFO1_EMPTY
FIFO1 (PCI to LOCAL) is empty of data. If there is more
data expected, the local processor must wait until this flag
is reset. If DMA1_COMPLETE and FIFO1_EMPTY are both
set the program can assume the whole block has now been
fetched.
FIFO2_FULL
FIFO2 (LOCAL to PCI) if full and no more data should be
written into it.
DMA1_ERROR
DMA2_ERROR
These flags indicate that an attempt to read or write the PCI
memory space failed for an non-recoverable reason. AB2061
regards PCI Master Abort (no device responds) and PCI
Target Abort events as non-recoverable.
Starting, Stopping and Resetting DMA
In order to get either DMA channel to re-read its BASE and LENGTH registers, the
appropriate ENABLE bit MUST be written as a '0'. To start a channel write the
BASE and LENGTH values, write a '0' to the ENABLE bit, followed immediately by
a '1'. Writing a 1 to a channel that is already running will not disturb its operation
in any way. To stop a channel in operation, write '0' to the appropriate ENABLE bit.
Note that this will STOP and RESET the channel. In order to pause without reset-
ting the counters and pointers write a '1' to the appropriate PAUSE bit. The pause
function will not stop a burst in progress once AB2061 has asserted REQuest to
the PCI bus.
DMA Channel 2 will normally only try to initiate a burst on the PCI bus when
FIFO2 is full (4 longwords). In cases where this is undesirable such as a block of
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