AB-2061G-33 Datasheet, PDF (27/32 Pages) List of Unclassifed Manufacturers – 33Mhz PCI to Local Bus Interface

DMA Controller Units
The DMA Controller units (DCUs) contain the control logic, pointers and counters
to schedule, sequence and provide source and destination addresses for data
passing through the FIFOs. These units ensure that the maximum burst length
possible is always used. In the case of AB2061 this is 4 longwords (32 bytes).
DMA transfers can be byte aligned within the PCI memory space, operation of this
feature is described in the DMA_MASK section.
AB2061 is not capable of directly placing data into a memory on the local bus. The
job of retrieving data from and writing data to the FIFOs is up to the local proces-
sor or some other DMA capable device. FIFO access has been specially optimised
to allow transfer to local memory by relatively simple DMA controllers such as
those present on many microcontroller devices.
Initialising DMA Transfers
DMA Channel 1 always moves data from the PCI memory space to the FIFOs and
hence into the local memory. Channel 2 moves data from local memory into PCI
memory space.
Channel1: DMA1_SOURCE_BASE Holds a 32 bit address. This is the first
location in the PCI memory space of the block
to be copied to local memory.
DMA1_LENGTH
This 16 bit register holds the length in
longwords of the block to be copied to local
memory.
Channel2: DMA2_DEST_BASE
Holds a 32 bit address. This is the first
location in the PCI memory space of the block
where data from local memory will be placed
DMA2_LENGTH
A 16 bit value which specifies the length of
the transfer in longwords.
DMA_MASK
This 8 bit value determines which bytes are
written in the first and last words of the block,
thus allowing blocks to be byte aligned.
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