AB-2061G-33 Datasheet, PDF (30/32 Pages) List of Unclassifed Manufacturers – 33Mhz PCI to Local Bus Interface

Non Aligned DMA Transfers
AB2061 supports the transfer of non word aligned blocks from the local processor
to PCI. Non aligned transfers from PCI to local are not supported however.
This feature is implemented through the DMA_MASK register which is 8 bits
wide. The lower nibble determines the pattern output on the PCI byte enables
when writing the first word of a block (and hence which bytes are written). The
upper nibble has the same effect on the last word of the block.
Example: To write the block shown below, the DMA_MASK register should be
written with the value 38h.
Byte_{111111111112222222222233333333333}3_{4444444444455555555555666666666667777777777788888888888}2_{999999999990000000000011111111111222222222223333333333344444444444}1_{55555555555666666666667777777777788888888888}0_{999999999990000000000011111111111}
0 = Byte written
DMA_MASK 0 0 1 1 1 0 0 0
111111111112222222222233333333333444444444445555555555566666666666777777777778888888888899999999999000000000001111111111122222222222333333333334444444444455555555555666666666667777777777788888888888999999999990000000000011111111111
Bit: 7 6 5 4 3 2 1 0
Shading indicates bytes to be transferred
Notes
1) It is possible to write non contiguous data with this feature, however this is
strongly discouraged and may result in some targets signalling a system
error on SERR.
2) When the local processor is writing data to the FIFO, it must always write
to FIFO_PCI_DATA4 last, regardless of whether that byte will be written in
the word. Failure to do this will result in the loss of the entire word of data.
3) When performing transfers of one word (or less), the upper and lower
nibbles of the DMA_MASK register should be written to the same value.