LM3S8938 Datasheet, PDF (74/550 Pages) List of Unclassifed Manufacturers – Microcontroller

System Control
Bit/Field
26:23
22
21:14
13
12
Name
SYSDIV
USESYSDIV
reserved
PWRDN
reserved
Type
R/W
R/W
RO
R/W
RO
Reset
0xF
0
1
1
1
Description
System Clock Divisor
Specifies which divisor is used to generate the system clock from the
PLL output.
The PLL VCO frequency is 400 MHz.
Binary Value Divisor (BYPASS=1) Frequency (BYPASS=0)
0000-0010 reserved
reserved
0011
/8
50 MHz
0100
/10
40 MHz
0101
/12
33.33 MHz
0110
/14
28.57 MHz
0111
/16
25 MHz
1000
/18
22.22 MHz
1001
/20
20 MHz
1010
/22
18.18 MHz
1011
/24
16.67 MHz
1100
/26
15.38 MHz
1101
/28
14.29 MHz
1110
/30
13.33 MHz
1111
/32
12.5 MHz (default)
When reading the Run-Mode Clock Configuration (RCC) register (see
page 73), the SYSDIV value is MINSYSDIV if a lower divider was
requested and the PLL is being used. This lower value is allowed to
divide a non-PLL source.
Use the system clock divider as the source for the system clock. The
system clock divider is forced to be used when the PLL is selected as
the source.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PLL Power Down
This bit connects to the PLL PWRDN input. The reset value of 1 powers
down the PLL.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
74
June 14, 2007
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