LM3S8938 Datasheet, PDF (217/550 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S8938 Microcontroller
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024
This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1
to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers.
GPTM Interrupt Clear (GPTMICR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x024
Type W1C, reset 0x0x0000.0000
31
30
29
28
Type RO
Reset
0
15
Type RO
Reset
0
RO
RO
RO
0
0
0
14
13
12
reserved
RO
RO
RO
0
0
0
27
26
25
24
23
reserved
RO
RO
RO
RO
RO
0
0
0
0
0
11
10
9
8
7
CBECINT CBMCINT TBTOCINT
RO
W1C W1C W1C
RO
0
0
0
0
0
22
21
RO
RO
0
0
6
5
reserved
RO
RO
0
0
20
19
18
17
16
RO
RO
RO
RO
RO
0
0
0
0
0
4
3
2
1
0
RTCCINT CAECINT CAMCINT TATOCINT
RO
W1C W1C W1C W1C
0
0
0
0
0
Bit/Field
31:11
10
9
8
7:4
3
2
1
Name
reserved
CBECINT
CBMCINT
TBTOCINT
reserved
RTCCINT
CAECINT
CAMCINT
Type
RO
W1C
W1C
W1C
RO
W1C
W1C
W1C
Reset
0
0
0
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM CaptureB Event Interrupt Clear
0: The interrupt is unaffected.
1: The interrupt is cleared.
GPTM CaptureB Match Interrupt Clear
0: The interrupt is unaffected.
1: The interrupt is cleared.
GPTM TimerB Time-Out Interrupt Clear
0: The interrupt is unaffected.
1: The interrupt is cleared.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM RTC Interrupt Clear
0: The interrupt is unaffected.
1: The interrupt is cleared.
GPTM CaptureA Event Interrupt Clear
0: The interrupt is unaffected.
1: The interrupt is cleared.
GPTM CaptureA Match Raw Interrupt
This is the CaptureA match interrupt status after masking.
June 14, 2007
217
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