LM3S8938 Datasheet, PDF (476/550 Pages) List of Unclassifed Manufacturers – Microcontroller

Ethernet Controller
Register 25: Ethernet PHY Management Register 17 – Interrupt Control/Status
(MR17), offset 0x11
This register provides the means for controlling and observing the events, which trigger a PHY
interrupt in the MACRIS register. This register can also be used in a polling mode via the MII Serial
Interface as a means to observe key events within the PHY via one register address. Bits 0 through
7 are status bits, which are each set to logic 1 based on an event. These bits are cleared after the
register is read. Bits 8 through 15 of this register, when set to logic 1, enable their corresponding
bit in the lower byte to signal a PHY interrupt in the MACRIS register.
Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17)
Base 0x4004.8000
Offset 0x11
Type R/W, reset 0x0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
JABBER_IE RXER_IE PRX_IE PDF_IE LPACK_IE LSCHG_IE RFAULT_IE ANEGCOMP_IE JABBER_INT RXER_INT PRX_INT PDF_INT LPACK_INT LSCHG_INT RFAULT_INT ANEGCOMP_NI T
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RC
RC
RC
RC
RC
RC
RC
RC
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:16
15
14
13
12
11
10
Name
reserved
JABBER_IE
RXER_IE
PRX_IE
PDF_IE
LPACK_IE
LSCHG_IE
Type
RO
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Jabber Interrupt Enable
When set, enables system interrupts when a Jabber condition is detected
by the PHY.
Receive Error Interrupt Enable
When set, enables system interrupts when a receive error is detected
by the PHY.
Page Received Interrupt Enable
When set, enables system interrupts when a new page is received by
the PHY.
Parallel Detection Fault Interrupt Enable
When set, enables system interrupts when a Parallel Detection Fault is
detected by the PHY.
LP Acknowledge Interrupt Enable
When set, enables system interrupts when FLP bursts are received with
the Acknowledge bit during Auto-Negotiation.
Link Status Change Interrupt Enable
When set, enables system interrupts when the Link Status changes
from OK to FAIL.
476
June 14, 2007
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