LM3S8938 Datasheet, PDF (213/550 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S8938 Microcontroller
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018
This register allows software to enable/disable GPTM controller-level interrupts. Writing a 1 enables
the interrupt, while writing a 0 disables it.
GPTM Interrupt Mask (GPTMIMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x018
Type R/W, reset 0x0x0000.0000
31
30
29
28
Type RO
Reset
0
15
Type RO
Reset
0
RO
RO
RO
0
0
0
14
13
12
reserved
RO
RO
RO
0
0
0
27
26
25
24
23
reserved
RO
RO
RO
RO
RO
0
0
0
0
0
11
10
9
8
7
CBEIM CBMIM TBTOIM
RO
R/W
R/W
R/W
RO
0
0
0
0
0
22
21
RO
RO
0
0
6
5
reserved
RO
RO
0
0
20
19
18
17
16
RO
RO
RO
RO
RO
0
0
0
0
0
4
3
2
1
0
RTCIM CAEIM CAMIM TATOIM
RO
R/W
R/W
R/W
R/W
0
0
0
0
0
Bit/Field
31:11
10
9
8
7:4
3
2
Name
reserved
CBEIM
CBMIM
TBTOIM
reserved
RTCIM
CAEIM
Type
RO
R/W
R/W
R/W
RO
R/W
R/W
Reset
0
0
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM CaptureB Event Interrupt Mask
0: Interrupt is disabled.
1: Interrupt is enabled.
GPTM CaptureB Match Interrupt Mask
0: Interrupt is disabled.
1: Interrupt is enabled.
GPTM TimerB Time-Out Interrupt Mask
0: Interrupt is disabled.
1: Interrupt is enabled.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM RTC Interrupt Mask
0: Interrupt is disabled.
1: Interrupt is enabled.
GPTM CaptureA Event Interrupt Mask
0: Interrupt is disabled.
1: Interrupt is enabled.
June 14, 2007
213
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