LM3S8938 Datasheet, PDF (444/550 Pages) List of Unclassifed Manufacturers – Microcontroller

Ethernet Controller
17.3
17.4
■ A frame has been received with one or more error conditions (e.g. FCS failed).
■ An MII management transaction between the MAC and PHY layers has completed.
■ One or more of the following PHY layer conditions occurs.
– Auto Negotiate Complete
– Remote Fault
– Link Status Change
– Link Partner Acknowledge
– Parallel Detect Fault
– Page Received
– Receive Error
– Jabber Event Detected
Initialization and Configuration
To use the Ethernet Controller, the peripheral must be enabled by setting the ETH bits in the RCGC2
register. The following steps can then be used to configure the ethernet controller for basic operation.
1. Program the MACDIV register to obtain a 2.5 MHz clock (or less) on the internal MII. Assuming
a 20 MHz system clock, the MACDIV value would be 4.
2. Program the MACIA0 and MACIA1 register for address filtering.
3. Program the MACTCTL register for Auto CRC generation, padding, and full duplex operation
using a value of 0x16.
4. Program the MACRCTL register to reject frames with bad FCS using a value of 0x08.
5. Enable both the Transmitter and Receive by setting the LSB in both the MACTCTL and
MACRCTL register.
6. To transmit a frame, write the frame into the TX FIFO using the MACDATA register. Then set
the NEWTX bit in the MACTR register to initiate the transmit process. When the NEWTX bit
has been cleared, the TX FIFO will be available for the next transmit frame.
7. To receive a frame, wait for the NPR field in the MACNP register to be non-zero. Then begin
reading the frame from the RX FIFO by using the MACDATA register. When the frame (including
the FCS field) has been read, the NPR field should decrement by one. When there are no more
frames in the RX FIFO, the NPR field will read 0.
Ethernet Register Map
Table 17-2 on page 445 lists the Ethernet MAC registers. All addresses given are relative to the
Ethernet MAC base address of 0x4004.8000.
The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY.
The registers are collectively known as the MII Management registers and are detailed in Section
444
June 14, 2007
Luminary Micro Confidential-Advance Product Information