LM3S8938 Datasheet, PDF (458/550 Pages) List of Unclassifed Manufacturers – Microcontroller

Ethernet Controller
Register 11: Ethernet MAC Management Divider (MACMDV), offset 0x024
This register enables software to set the clock divider for the Management Data Clock (MDC). This
clock is used to synchronize read and write transactions between the system and the MII Management
registers. The frequency of the MDC clock can be calculated from the following formula:
F_mdc = F_ipclk / (2 * (MACMDVR + 1 ))
The clock divider must be written with a value that ensures that the MDC clock will not exceed a
frequency of 2.5 MHz.
Ethernet MAC Management Divider (MACMDV)
Base 0x4004.8000
Offset 0x024
Type R/W, reset 0x0000.0080
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DIV
Type RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Bit/Field
31:8
7:0
Name
reserved
DIV
Type
RO
R/W
Reset
0x0
0x80
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
The DIV bits are used to set the clock divider for the MDC clock used
to transmit data between the MAC and PHY over the serial MII interface.
458
June 14, 2007
Luminary Micro Confidential-Advance Product Information