SMH4046 Datasheet, PDF (5/51 Pages) List of Unclassifed Manufacturers – Hot-Swap, Active DC Output Control (ADOCTM) Power Manager with I2C lnterface

PIN DESCRIPTIONS
SMH4046
Preliminary Information
Symbol
Pin Type
Description
SCL
A2
HST_RST
HST_PWR
FS
EXT_TEMP
IRQ#
RESET (RST)
FAULT
HEALTHY
GND
PND1#
PND2#
CARD_V_VLD
VMA
1
I The I²C serial bus clock.
2
I An external address bit for I²C.
Host reset. This input is the reset signal from the host interface. Asserting this
3
I pin causes a reset sequence to be performed on the card. Programmable
polarity.
Host power-up enable. This input provides the host system with active control
over the sequencing of the power up operation. When de-asserted, the
4
I
SMH4046 holds the add-in card in reset and blocks all power to the back-end
logic. When HST_PWR is asserted, the power sequencing begins immediately
and the reset output is driven active after the time tPURST. Programmable
polarity.
5
I
Force Shutdown. This programmable active high/low input is used to
immediately turn off all converter enable signals and external FETs.
6
I
This input can be used to sense a voltage generated from an external
temperature monitoring device.
7
O
Active low Interrupt output. Generated by the SMH4046 on an error condition.
This signal can be used by external logic to interrupt the host.
8
O
RESET is a programmable active high/low open drain output that is asserted
by the SMH4046 when a programmed reset condition occurs.
9
O
FAULT is a programmable active high/low open drain fault output that is
asserted by the SMH4046 when a programmed fault condition occurs.
10
O
Healthy is a programmable active high/low open drain output that is asserted
by the SMH4046 when all programmed healthy conditions are met.
11 PWR Ground.
Pin detect 1 is an active low CMOS level input. In conjunction with PND2#,
this signal indicates proper card insertion when taken low. This pin must be
12
I
connected to ground on the host side of the connector. PND1# and PND2#
should be placed on opposite corners of the connector and will preferably be
staggered shorter than the power connector pins. Board insertion is assumed
when PND1# and PND2# are low.
Pin detect 2 is an active low CMOS level input. In conjunction with PND1#,
this signal indicates proper card insertion when taken low. This pin must be
13
I
connected to ground on the host side of the connector. PND1# and PND2#
should be placed on opposite corners of the connector and will preferably be
staggered shorter than the power connector pins. Board insertion is assumed
when PND1# and PND2# are low.
14
O
Card voltage valid. This open drain output indicates that the card side voltages
are at or above their respective trip levels. Active high.
15 I Positive converter sense line for DC/DC converter A
TRIMA
TRIM_CAPA
16 O Output voltage used to control the output of DC/DC converter A.
17
I
External sample and hold capacitor input used to set the voltage on the
TRIMA pin.
Summit Microelectronics, Inc
2082 1.7 08/23/04
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