SMH4046 Datasheet, PDF (19/51 Pages) List of Unclassifed Manufacturers – Hot-Swap, Active DC Output Control (ADOCTM) Power Manager with I2C lnterface

I²C 2-WIRE SERIAL INTERFACE (CONTINUED)
SMH4046
Preliminary Information
Figure 16 - Typical EE Memory Write and Random Read Operations
FPGA Configuration Interface
The FPGA interface is used to perform configuration of
industry standard FPGAs by loading application
specific data into the FPGA configuration memory via
the SMH4046 FPGA interface. To enable the FPGA
interface option, Bit 7 of configuration register hex0C
must be set to a 1. Bits [2:0] of register hex84, slave
address 1001are write/read bits that are mapped to
output pins FPGA_DCLK, FPGA_DO, and
FPGA_NCFG, respectively.
A write to these bits will result in the same
corresponding state on the output pins. Bits [7:6] are
mapped to input pins FPGA_NSTS and
FPGA_CFGDONE, respectively. The state of these
pins is reflected in the corresponding bits and can be
read. The function of each pin is described in Table 1.
For more information, see the FPGA data sheet for
configuration options.
Symbol
Type Description
FPGA_NSTS
FPGA_CFGD
ONE
FPGA_NCFG
FPGA_DO
FPGA_DCLK
I FPGA configuration status input pin
I FPGA_CFGDONE indicates completion of the configuration process.
O
FPGA_NCFG is a configuration control output. A low transition resets the target
device; a low-to-high transition begins configuration.
O
FPGA_DO provides preamble and configuration data to downstream devices in a
daisy-chain.
O
FPGA Configuration clock output. Clock output used to clock configuration data
using pin FPGA_DO.
TABLE 1 – FPGA Configuration interface
Summit Microelectronics, Inc
2082 1.7 08/23/04
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