SMH4046 Datasheet, PDF (17/51 Pages) List of Unclassifed Manufacturers – Hot-Swap, Active DC Output Control (ADOCTM) Power Manager with I2C lnterface

I²C 2-WIRE SERIAL INTERFACE
Programming Information
I²C Bus Interface
The I²C bus interface is a standard two-wire serial
protocol that allows communication between
integrated circuits. The data line (SDA) is a bi-
directional I/O; the clock line (SCL) runs at speeds of
up to 400kHz. The SMH4046 supports a 100 kHz
clock rate. The SDA line must be connected to a
positive logic supply through a pull-up resistor located
on the bus.
Start and Stop Conditions
Both the SDA and SCL pins remain high when the bus
is not busy. Data transfers between devices may be
initiated with a Start condition. A high-to-low transition
of the SDA input while the SCL pin is high is defined
as a Start condition. A low-to-high transition SDA while
SCL is high is defined as a Stop condition. Figure 11
shows a timing diagram of the start and stop
conditions.
SMH4046
Preliminary Information
Acknowledge
Data is always transferred in bytes. Acknowledge
(ACK) is used to indicate a successful data transfer.
The transmitting device releases the bus after
transmitting eight bits. During the ninth clock cycle the
Receiver pulls the SDA line low to acknowledge that it
received the eight bits of data. This is shown by the
ACK callout in Figure 12.
When the last byte has been transferred to the Master
during a read of the SMH4046, the Master leaves SDA
high for a Not Acknowledge (NACK) cycle. This
causes the SMH4046 part to stop sending data, and
the Master issues a Stop on the clock pulse following
the NACK.
Figure 11 - Start and Stop Conditions
Master/Slave Protocol
The master/slave protocol defines any device that
sends data onto the bus as a transmitter, and any
device that receives data as a receiver. The device
controlling data transmission is called the Master, and
the controlled device is called the Slave. In all cases
the SMH4046 is referred to as a Slave device since it
never initiates any data transfers. One data bit is
transferred during each clock pulse. The data on the
SDA line must remain stable during clock high time,
because a change on the data line while SCL is high is
interpreted as either a Start or a Stop condition.
Figure 12 - Acknowledge Timing
Read and Write
The first byte from a Master is always made up of a 7-
bit Slave address and the Read/Write (R/W) bit. The
R/W bit tells the Slave whether the Master is reading
data from the bus or writing data to the bus (1 = Read,
0 = Write). The first four of the seven address bits are
called the Device Type Identifier (DTI). In the case of
the SMH4046, the next two bits are Bus Address
values, used to distinguish multiple devices on a
common bus. The seventh bit of the slave address
represents the ninth bit of the word address. The
SMH4046 issues an Acknowledge after recognizing a
Start condition and its DTI. Figure 13 shows an
example of a typical master address byte
transmission.
Figure 13 - Typical Master Address Byte
Transmission
Summit Microelectronics, Inc
2082 1.7 08/23/04
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