SMH4046 Datasheet, PDF (25/51 Pages) List of Unclassifed Manufacturers – Hot-Swap, Active DC Output Control (ADOCTM) Power Manager with I2C lnterface

CONFIGURATION REGISTERS
SMH4046
Preliminary Information
Configuration Registers:
The configuration registers are accessible via the I²C
interface at slave address 1010 or 1011 and 1001.
These registers determine which features of the
device are active, set voltage sensing threshold levels,
and define the programmable output logic.
The following tables describe the configuration register
bits in detail. The following registers are accessed
using slave address 101 SA0 A2 A1 1 (SA0 =
C_0E[3]).
Register R00 – VREF nominal settings.
Bits D[7:6] are unused and should be set to 00. Bits D[5:4] control the Ch C VREF value. Bits D[3:2] control Ch B
VREF and Bits D[1:0] control Ch A VREF.
Register R00
D7 D6 D5 D4 D3 D2 D1 D0
Action
0
0
-
-
-
-
-
- Unused.
-
-
0
0
-
-
-
- Ch C VREF=0.75 V
-
-
0
1
-
-
-
- Ch C VREF=1.0 V
-
-
1
0
-
-
-
- Ch C VREF=1.25 V
-
-
1
1
-
-
-
- Ch C VREF=2.0 V
-
-
-
-
1
1
-
- Ch B VREF selection Nominal
-
-
-
-
-
-
1
1 Ch A VREF selection Nominal
Register R01 – Channel A Nominal Setting.
Bits D[7:0] control the Channel A Margin Nominal setting. The DC Control Voltage setting bits (C[7:0]) are set using
C[7:0] = 256 * VREF_CNTL / DC Control Voltage. VREF_CNTL is from register R00.
Register R01
D7 D6 D5 D4 D3 D2 D1 D0
Action
C7 C6 C5 C4 C3 C2 C1 C0 ^{Channel A Margin Nominal Bits [7:0]}
Register R02 – Channel C Nominal Setting.
Bits D[7:0] control the Channel C Margin Nominal setting
Register R02
D7 D6 D5 D4 D3 D2 D1 D0
C7 C6 C5 C4 C3 C2 C1 C0
Action
Channel C Margin Nominal Bits [7:0]
Register R03 – Channel B Nominal Setting.
Bits D[7:0] control the Channel B Margin Nominal setting
Register R03
D7 D6 D5 D4 D3 D2 D1 D0
C7 C6 C5 C4 C3 C2 C1 C0
Action
Channel B Margin Nominal Bits [7:0]
Summit Microelectronics, Inc
2082 1.7 08/23/04
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