SMH4046 Datasheet, PDF (33/51 Pages) List of Unclassifed Manufacturers – Hot-Swap, Active DC Output Control (ADOCTM) Power Manager with I2C lnterface

CONFIGURATION REGISTERS (CONTINUED)
SMH4046
Preliminary Information
Register R30 – VREF Margin Channels A-C.
Register R30
D7 D6 D5 D4 D3 D2 D1 D0
Action
0
-
-
-
-
-
-
- Unused
-
0
-
-
-
-
-
- Unused
-
-
0
0
-
-
-
- Channel C VREF Margin High Selection = 0.75V
-
-
0
1
-
-
-
- Channel C VREF Margin High Selection = 1.00V
-
-
1
0
-
-
-
- Channel C VREF Margin High Selection = 1.25V
-
-
1
1
-
-
-
- Channel C VREF Margin High Selection = 2.00V
-
-
-
-
0
0
-
- Channel B VREF Margin High Selection = 0.75V
-
-
-
-
0
1
-
- Channel B VREF Margin High Selection = 1.00V
-
-
-
-
1
0
-
- Channel B VREF Margin High Selection = 1.25V
-
-
-
-
1
1
-
- Channel B VREF Margin High Selection = 2.00V
-
-
-
-
-
-
0
0 Channel A VREF Margin High Selection = 0.75V
-
-
-
-
-
-
0
1 Channel A VREF Margin High Selection = 1.00V
-
-
-
-
-
-
1
0 Channel A VREF Margin High Selection = 1.25V
-
-
-
-
-
-
1
1 Channel A VREF Margin High Selection = 2.00V
Register R31 – Channel A Margin High bits
Register R31
D7 D6 D5 D4 D3 D2 D1
C7 C6 C5 C4 C3 C2 C1
D0
Action
C0 Channel A Margin High Bits [7:0]
Register R32 – Channel C Margin High bits
Register R32
D7 D6 D5 D4 D3 D2 D1
C7 C6 C5 C4 C3 C2 C1
D0
Action
C0 Channel C Margin High Bits [7:0]
Register R33 – Channel B Margin High bits
Register R33
D7 D6 D5 D4 D3 D2 D1
C7 C6 C5 C4 C3 C2 C1
D0
Action
C0 Channel B Margin High Bits [7:0]
Summit Microelectronics, Inc
2082 1.7 08/23/04
33