SMH4046 Datasheet, PDF (34/51 Pages) List of Unclassifed Manufacturers – Hot-Swap, Active DC Output Control (ADOCTM) Power Manager with I2C lnterface

CONFIGURATION REGISTERS (CONTINUED)
SMH4046
Preliminary Information
Register R40 – VREF Margin Channels A-C.
Register R40
D7 D6 D5 D4 D3 D2 D1 D0
Action
0
-
-
-
-
-
-
- Unused
-
0
-
-
-
-
-
- Unused
-
-
0
0
-
-
-
- Channel C VREF Margin Low Selection = 0.75V
-
-
0
1
-
-
-
- Channel C VREF Margin Low Selection = 1.00V
-
-
1
0
-
-
-
- Channel C VREF Margin Low Selection = 1.25V
-
-
1
1
-
-
-
- Channel C VREF Margin Low Selection = 2.00V
-
-
-
-
0
0
-
- Channel B VREF Margin Low Selection = 0.75V
-
-
-
-
0
1
-
- Channel B VREF Margin Low Selection = 1.00V
-
-
-
-
1
0
-
- Channel B VREF Margin Low Selection = 1.25V
-
-
-
-
1
1
-
- Channel B VREF Margin Low Selection = 2.00V
-
-
-
-
-
-
0
0 Channel A VREF Margin Low Selection = 0.75V
-
-
-
-
-
-
0
1 Channel A VREF Margin Low Selection = 1.00V
-
-
-
-
-
-
1
0 Channel A VREF Margin Low Selection = 1.25V
-
-
-
-
-
-
1
1 Channel A VREF Margin Low Selection = 2.00V
Register R41 – Channel A Margin Low bits
Register R41
D7 D6 D5 D4 D3 D2 D1
C7 C6 C5 C4 C3 C2 C1
D0
Action
C0 Channel A Margin Low Bits [7:0]
Register 42 – Channel C Margin Low bits
Register R42
D7 D6 D5 D4 D3 D2 D1 D0
Action
C7 C6 C5 C4 C3 C2 C1 C0 Channel C Margin Low Bits [7:0]
Register R43 – Channel B Margin Low bits
Register R43
D7 D6 D5 D4 D3 D2 D1
C7 C6 C5 C4 C3 C2 C1
D0
Action
C0 Channel B Margin Low Bits [7:0]
Summit Microelectronics, Inc
2082 1.7 08/23/04
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