SMH4046 Datasheet, PDF (18/51 Pages) List of Unclassifed Manufacturers – Hot-Swap, Active DC Output Control (ADOCTM) Power Manager with I2C lnterface

I²C 2-WIRE SERIAL INTERFACE (CONTINUED)
During a read by the Master device, the SMH4046
transmits eight bits of data, then releases the SDA
line, and monitors the line for an Acknowledge signal.
If an Acknowledge is detected, and no Stop condition
is generated by the Master, the SMH4046 continues to
transmit data. If an Acknowledge is not detected
(NACK), the SMH4046 terminates any subsequent
data transmission. The read transfer protocol on SDA
is shown in Figure 14.
Figure 14 - Read Protocol
During a Master write, the SMH4046 receives eight
bits of data, then generates an Acknowledge signal.
The device continues to generate the ACK condition
on SDA until a Stop condition is generated by the
Master. The write transfer protocol on SDA is shown in
Figure 15.
Figure 15 - Write Protocol
SMH4046
Preliminary Information
Random Access Read
Random address read operations (Figure 16) allow the
Master to access any memory location in a random
fashion. This operation involves a two-step process.
First, the Master issues a Write command which
includes the Start condition and the Slave address
field (with the R/W bit set to Write) followed by the
address of the word it is to read. This procedure sets
the internal address counter of the SMH4046 to the
desired address.
After the word address Acknowledge is received by
the Master, it immediately reissues a Start condition
followed by another Slave address field with the R/W
bit set to Read. The SMH4046 responds with an
Acknowledge and then transmits the 8 data bits stored
at the addressed location. At this point, the Master
sets the SDA line to NACK and generates a Stop
condition. The SMH4046 discontinues data
transmission and reverts to its standby power mode.
Sequential Reads
Sequential reads (Figure 16) can be initiated as either
a current address read or a random access read. The
first word is transmitted as with the other byte Read
modes (current address byte Read or random address
byte Read). However, the Master now responds with
an Acknowledge, indicating that it requires additional
data from the SMH4046.
The SMH4046 continues to output data for each
Acknowledge received. The Master sets the SDA line
to NACK and generates a Stop condition. During a
sequential Read operation the internal address
counter is automatically incremented with each
Acknowledge signal.
For Read operations all address bits are incremented,
allowing the entire array to be read using a single
Read command. After a count of the last memory
address the address counter rolls over and the
memory continues to output data.
Summit Microelectronics, Inc
2082 1.7 08/23/04
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