ES1371 Datasheet, PDF (5/37 Pages) List of Unclassifed Manufacturers – ENSONIQ AudioPCI 97 digital controller

ENSONIQ Proprietary Information
4.8. UART
This block includes both the transmitter and receiver for the AudioPCI 97 MIDI interface. The UART
controller also implements an eight byte FIFO in the internal memory. This FIFO is then accessed through
the HOST interface block.
4.9. Sample Rate Converter
This block receives or sends samples from/to the serial interface block for the playback/record channels.
The Sample Rate converter block converts two variable input rate playback channels to one fixed rate
(48Khz) output channel. It also takes one fixed input rate (48Khz) record channel and converts it to a
variable rate output channel. The channels are programmed by writing several ram locations that are a
function of the input and output rates. The Sample Rate Converter block has it’s own memory section. The
Sample Rate Converter memory is accessible only by the Sample Rate Converter block.
Sample Rate Converter Flow
Synth & Wave
Channels
4k-48k Stereo
Codec 48K
Codec 48K
Linear
N
FIR
Interp
Filter
olate _{Record Data}
4k-48k
The first stage consists of expanding the number of input samples by an integer number (N), up to a
maximum of 16, and filling in between the samples with zeros. Then the new samples are filtered by a long
1/32 band FIR filter. In practice, the zeros are not multiplied with their corresponding FIR coefficients.
The input samples are fed into an input FIFO and the hardware figures out which FIR coefficient
corresponds to each FIFO sample. The starting coefficient and the spacing between successive coefficients
are calculated by aligning the FIR filter with a virtual FIFO which is the expanded version of the real FIFO.
The coefficient positions also depend on the third stage in the block diagram, the linear interpolator. This
interpolator uses frequency and accumulator registers to interpolate between 2 samples.
4.10. Memory Bus
This pathway is used exclusively to transfer data between the internal sound cache memory and the various
sub-systems. The access priority for this bus is (highest to lowest):
Cache Control block
Host Interface
UART Interface
Serial Interface
ENSONIQ Proprietary Information
ENSONIQ AudioPCI 97 Specification Rev 1.1 Oct 1, 1997
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