ES1371 Datasheet, PDF (23/37 Pages) List of Unclassifed Manufacturers – ENSONIQ AudioPCI 97 digital controller

ENSONIQ Proprietary Information
18
R/W SBCAP
17
R/W CDCCAP
16
R/W BACAP
15:11 R
10:8 R
ONE
E2, E1, E0
7:3 R A[4:0]
2
R W/R
1
R ZERO
0
R/W INT#
1 - Enables event capture
This bit enables event capture for the SoundBlaster registers. The
decoded address range for this event is selected by the VSB control
bit.
0 - Disables event capture
1 - Enables event capture
This bit enables event capture for the CODEC. The decoded address
range for this event is selected by the VCDC[1:0] control bits.
0 - Disables event capture
1 - Enables event capture
This bit enables event capture for the SoundScape Base Address
register. The decoded address range for this event is selected by the
VMPU[1:0] control bits.
0 - Disables event capture
1 - Enables event capture
These bits will always read back as ones
These three bits are the event number of the captured event. The
event number corresponds to the enable bit which allowed the
interrupt. Their decoding is shown below:
000 - SoundScape Base Address
001 - CODEC
010 - SoundBlaster Registers
011 - ADLIB Registers
100 - Master Interrupt Controller
101 - Master DMA Controller
110 - Slave Interrupt Controller
111 - Slave DMA Controller
These bits are the least significant I/O address bits during the event
captured.
This bit indicates whether the event captured was a read or write
operation.
0 - Event captured was a Read
1 - Event captured was a Write
This bit always reads back as a zero.
This bit is the interrupt flag for LEGACY events. A write to this bit
(0 or 1) resets the interrupt flag.
0 - Interrupt did occur
1 - Interrupt did not occur
ENSONIQ Proprietary Information
ENSONIQ AudioPCI 97 Specification Rev 1.1 Oct 1, 1997
23