ES1371 Datasheet, PDF (4/37 Pages) List of Unclassifed Manufacturers – ENSONIQ AudioPCI 97 digital controller

ENSONIQ Proprietary Information
4. THE SYSTEM Components
4.1. PCI Interface/LEGACY
The PCI subsystem is a bus master interface that performs the memory accesses to keep the Audio cache
buffers full and empties the A/D Converter (or I2S input) buffer to main memory as required.
All system control registers are accessed via I/O on the PCI bus. AudioPCI 97 uses 16 Long Words in the
I/O space for control registers. All registers are read as Long Words. All registers are written in byte word
or longword format.
The PCI block also includes the functions necessary to provide legacy mode support. This block generates
IRQ or SERR# at a specified ADLib access, SoundBlaster access, DMA controller access, IRQ (PIC)
controllers access, Microsoft WSS access, or Soundscape access.
4.2. Bus Master Cache Control (CCB)
This block controls the transfer of data between the PCI memory and the internal memory. The Serial block
signals when a cache fill/transfer is required in the three memory buffers. The CCB calculates the PCI
address from the frame data and issues a command to the PCI interface. When the PCI interface signals that
the data is available the CCB channels the data to the proper place in memory. This block is functionally
equivalent to a 3 channel DMA controller.
4.3. Serial Interface
This block performs a parallel transfer to/from the internal memory for the record and playback channels
respectfully. The record channel source can be either the I2S inputs or the AC97 CODEC ADC serial input
signal. This block also signals the CCB block when a cache fill/transfer is required.
4.4. Host Interface
This block arbitrates a PCI access to the internal memory. When the data transfer is complete, it responds
with an acknowledge to the PCI interface block. This block provides direct access to the internal memory. It
can be used to access the playback/record channels cache, the UART FIFO or the CCB registers.
4.5. CODEC Controller
This block reads/writes configuration data from the host bus to the AC97 CODEC using the serial protocol
of the AC97 CODEC. This block also merges the mixed playback channel data into the AC97 CODEC’s
serial data input, and it retrieves the record channel data from the AC97 CODEC’s serial data output.
4.6. IRQ & Chip Select Block
The functions for this block are:
1. Decode the internal address bus to generate chip selects to each block.
2. Contains internal registers whose outputs are control bits used by internal blocks for control/selection.
3. Summarizes all system IRQ’s (UART, CODEC, etc.) to generate a single AudioPCI 97 IRQ to the host.
This also includes the playback and record DMA channels. Any IRQ masking is performed within the
individual blocks except for the CCB block interrupt.
4.7. Joystick
This block contains the logic required to implement the joystick interface for AudioPCI 97.
ENSONIQ Proprietary Information
ENSONIQ AudioPCI 97 Specification Rev 1.1 Oct 1, 1997
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