ES1371 Datasheet, PDF (22/37 Pages) List of Unclassifed Manufacturers – ENSONIQ AudioPCI 97 digital controller

ENSONIQ Proprietary Information
7.6. Legacy
The Legacy register is a 32 bit register that performs both control and status functions. Basically the
lower word functions as the status register and the upper word functions as the control register. The only
exception to this is bit zero which is a control bit for a write and a status bit for a read.
Legacy Control/Status Register
Address 18H
Addressable as byte, word, longword
Power on reset value 00?????00000000011111?????????0?b
Direct Mapped
Bit(s) R/W Name
Function
31
R/W JFAST
This bit selects fast (vs ISA) joystick timing.
0 - ISA joystick timing
1 - FAST joystick timing
30
R/W HIB
This bit is the host interrupt blocking enable bit (DMA config bit
must be set) to prevent applications from blocking NMI.
0 - Host interrupt blocking disabled
1 - Host interrupt blocking enabled
29
R/W VSB
This bit selects the capture address range for SoundBlaster access.
0 - Address range : 220xH - 22FxH
1 - Address range : 240xH - 24FxH
28:27 R/W VMPU[1:0]
These bits select the capture address range for the Base Register.
00 - Address range : 320xH - 327xH
01 - Address range : 330xH - 337xH
10 - Address range : 340xH - 347xH
11 - Address range : 350xH - 357xH
26:25 R/W VCDC[1:0]
These bits select the capture address range for the CODEC.
00 - Address range : 530xH - 537xH
01 - Undefined
10 - Address range : E80xH - E87xH
11 - Address range : F40xH - F47xH
24
R/W FIRQ
This bit is used to force an interrupt.
0 - Do not force an interrupt
1 - Force an interrupt
23
R/W SDMACAP
This bit enables event capture for the Slave DMA Controller. The
decoded address range for this event is C0xH - DFxH.
0 - Disables event capture
1 - Enables event capture
22
R/W SPICAP
This bit enables event capture for the Slave Interrupt Controller.
The decoded address range for this event is A0xH - A1xH.
0 - Disables event capture
1 - Enables event capture
21
R/W MDMACAP
This bit enables event capture for the Master DMA Controller. The
decoded address range for this event is 0xH - FxH.
0 - Disables event capture
1 - Enables event capture
20
R/W MPICAP
This bit enables event capture for the Master Interrupt Controller.
The decoded address range for this event is 20xH - 21xH.
0 - Disables event capture
1 - Enables event capture
19
R/W ADCAP
This bit enables event capture for the ADLIB registers . The
decoded address range for this event is 388xH - 38BxH.
0 - Disables event capture
ENSONIQ Proprietary Information
ENSONIQ AudioPCI 97 Specification Rev 1.1 Oct 1, 1997
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