ES1371 Datasheet, PDF (24/37 Pages) List of Unclassifed Manufacturers – ENSONIQ AudioPCI 97 digital controller

ENSONIQ Proprietary Information
7.7. Serial Interface
There is one 16 bit control register and three 32 bit control/status registers in the serial block. The 16 bit
control register can be read or written. The three 32 bit control/status registers can be read or written but
only the lower 16 bits can actually be written. The upper 16 bits of these registers provides the status of the
internal sample counter.
Serial Interface Control Register
Address 20H
Addressable as byte, word, longword
Power on reset value FF800000H
Direct Mapped
Bit(s) R/W Name
Function
31:23 R/W ONES
These bits always read back as ones. They are not writable.
22
R/W DAC_TEST
This bit is used for testing purposes. It will select the I2S lrclk input
signal as the source for the playback and record channels. It is used
for test vector generation purposes only.
0 - DAC test mode disabled.
1 - DAC test mode enabled.
21:19 R/W P2_END_INC[2:0] These bits are the binary offset value that will be added to the
sample address counter at the end of the loop. This value is used
only if the DAC2 channel is in loop mode; it is not used in stop
mode. If loop mode is selected this value must be greater than zero
otherwise the channel will not function correctly. This minimum
value will be one if 8 bit mode is selected and two if 16 bit mode is
selected.
18:16 R/W P2_ST_INC[2:0] These bits are the binary offset value that will be added to the
sample address counter when the channel is started/restarted. This
value can be zero and will allow the sample fetch to start on any
byte boundary. For 16 bit data this value must be an even number.
15
R/W R1_LOOP_SEL This bit selects loop/stop mode for the ADC channel. This bit
determines what action the channel will perform when the sample
count reaches zero.
0 - Loop mode ; interrupt set (if enabled) but keeps recording
1 - Stop mode ; interrupt set (if enabled) , stops recording
14
R/W P2_LOOP_SEL This bit selects loop/stop mode for the DAC2 channel. This bit
determines what action the channel will perform when the sample
count reaches zero.
0 - Loop mode ; interrupt set (if enabled) but keeps playing
1 - Stop mode ; interrupt set (if enabled) , plays last sample
13
R/W P1_LOOP_SEL This bit selects loop/stop mode for the DAC1 channel. This bit
determines what action the channel will perform when the sample
count reaches zero.
0 - Loop mode ; interrupt set (if enabled) but keeps playing
1 - Stop mode ; interrupt set (if enabled) , plays last sample
12
R/W P2_PAUSE
This bit selects pause mode for the DAC2 playback channel. When
in pause mode the channel will playback the last sample.
0 - Play mode ; normal playback mode or removes channel
from pause mode on next sample after bit is
cleared
1 - Pause mode ; plays last sample continuously on next sample
after the pause bit has been set
11
R/W P1_PAUSE
This bit selects pause mode for the DAC1 playback channel. When
ENSONIQ Proprietary Information
ENSONIQ AudioPCI 97 Specification Rev 1.1 Oct 1, 1997
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