ES1371 Datasheet, PDF (15/37 Pages) List of Unclassifed Manufacturers – ENSONIQ AudioPCI 97 digital controller

ENSONIQ Proprietary Information
7.1. IRQ & Chip Select Block
The IRQ/Chip Select block contains two 32 bit registers. The first register is the control register which can
be read and written. The second register is the status register which is a read only register. The control
registers includes bits for module enables, interrupt control, general purpose I/O pins and power
management functions.
Interrupt/Chip Select Control Register
Address 00H
Addressable as byte, word, longword
Power on reset value FCxF0000H
Direct Mapped
Bit(s) R/W Name
Function
31:26 R ONES
These bits are not implemented and read back as ones.
25:24 R/W JOY_ASEL[1:0] These two bits are dedicated to Dave Sowa and will map the
joystick port to 4 different base addresses as follows:
00 - Joystick base address $200
01 - Joystick base address $208
10 - Joystick base address $210
11 - Joystick base address $218
23:20 R GPIO_IN[3:0]
These bits will read the current value on the GPIO [3:0] pins.
19:16 R/W GPIO_OUT[3:0] These bits when set low will set the corresponding GPIO output
low. If these bits are set high then the GPIO pads will be high or
they can be used as inputs.
15
R/W MSFMTSEL
This bit selects the MPEG serial data format.
0 - SONY (lrclk high = left channel ; data left justified)
1 - I2S (lrclk low = left channel ; data 1 bit clock delayed)
14
R/W SYNC_RES
This bit is used to generate a Warm AC97 Reset as described in
section 5.2.1.2. of the Audio Codec 97 specification.
13
R/W ADC_STOP
This bit when set high will prevent the CCB module from doing a
record channel PCI transfer.
0 - CCB will transfer record information.
1 - CCB will not transfer record information.
12
R/W PWR_INTRM
This bit selects is the interrupt mask bit for detecting changes in the
power management level.
0 - Power level change interrupts are disabled.
1 - Power level change interrupts are enabled.
11
R/W M_CB
This bit selects either I2S or the CODEC ADC as the source for the
record channel in the serial module.
0 - CODEC ADC is record channel source.
1 - I2S is record channel source.
10
R/W CCB_INTRM
This bit is the interrupt mask bit for the CCB module voice
interrupts.
0 - CCB voice interrupts are disabled.
1 - CCB voice interrupts are enabled.
9:8 R/W PDLEV[1:0]
Current power down level. These bits reflect the power down level
the part is currently programmed to. When the Power State bits
programmed in configuration space differs from these bits, an
interrupt is generated. The ISR should program this to equal the
value in configuration space in order to clear the interrupt.
00 - D0
01 - D1
10 - D2
11 - D3
ENSONIQ Proprietary Information
ENSONIQ AudioPCI 97 Specification Rev 1.1 Oct 1, 1997
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