ES1371 Datasheet, PDF (10/37 Pages) List of Unclassifed Manufacturers – ENSONIQ AudioPCI 97 digital controller

ENSONIQ Proprietary Information
Status
Addressable as word
Power on reset value x610H
Bit(s) R/W Name
15
R PARITY
14
R SERR#
13
R MASTER-ABORT
12
R TARGET-ABORT
11
R
10:9 R
ZERO
DEVSEL#
8:5 R ZERO
4
R CAPABILITIES
3:0 R ZERO
Address 06H
Configuration Space
Data Value
Parity Error status bit.
0 - No Parity error.
1 - Parity error detected.
SERR# PCI bus signal active status bit. This bit will be set if the
AudioPCI 97 ASIC is asserting the PCI SERR# signal.
0 - SERR# signal inactive.
1 - SERR# signal active.
Master Abort status bit. This bit will be set whenever a AudioPCI
97 ASIC bus mastering transaction has been terminated by a
Master-Abort.
Target Abort status bit. This bit will be set whenever a AudioPCI 97
ASIC bus mastering transaction has been terminated by a Target-
Abort.
This status bit is not implemented and always reads back as zero.
DEVSEL# timing. These status bits encode the timing of the PCI
DEVSEL# signal. AudioPCI 97 implements the slow timing mode.
00 - Fast
01 - Medium
10 - Slow
11 - Reserved
These status bits are not implemented and always read back as
zeros.
Indicates support for ACPI. The AudioPCI 97 ASIC does support
ACPI so this bit is set to a one.
These status bits are reserved and always read back as zeros.
Class Code & Revision ID
Addressable as long word
Power on reset value 04010000H
Bit(s) R/W Name
31:8 R CLASS CODE
7:0 R REVISION ID
Data Value
040100H (Multimedia Audio device)
02H
Address 08H
Configuration Space
ENSONIQ Proprietary Information
ENSONIQ AudioPCI 97 Specification Rev 1.1 Oct 1, 1997
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