ES1371 Datasheet, PDF (31/37 Pages) List of Unclassifed Manufacturers – ENSONIQ AudioPCI 97 digital controller

ENSONIQ Proprietary Information
10. PIN DESCRIPTION
10.1. PCI Interface
The PCI Interface follows the information presented on the PCI Local Bus Specification Revision 2.2. For
a more complete description of each of the PCI signal please refer to the PCI specification.
CLK
Clock: A 33MHz input signal from the PCI bus. This is the master timing control for all
PCI transfers.
RST#
Reset: The device will essentially be in sleep mode after reset.
AD[31:0]
The Address/Data multiplexed signals of the PCI Bus.
C/BE#[3:0] Bus Command and Byte Enables. Defines the type of transfer that will take place.
FRAME#
Cycle Frame. Driven by the current bus master, this signal indicates the beginning of a
transfer. When FRAME# is deasserted, the transaction is in the final phase.
IRDY#
Initiator Ready. This signal indicates that the initiating agent (the bus master) is able to
accept the data phase of the transaction. Normally used to create wait states by the
master.
TRDY#
Target Ready. Driven by the target (the selected device), this signal indicates that the
target is ready for the data transaction. Generally used to generate wait states by the
target.
STOP#
Stop indicates the current target is requesting the master to stop the current transaction.
SERR#
System Error. This pin is an output only pin on the ES1371.
PAR
The Parity signal is even parity. The number of “1”s on AD[31:0],C/BE[3:0] and Par
equal an even number.
IDSEL
Initialization Device Select. This signal is used as a chip select during configuration read
and write transactions
DEVSEL#
Device Select. This signal, when actively driven, indicates that the driving device has
decoded its address as the target of the current transaction.
REQ#
Request indicates to the arbiter that AudioPCI 97 desires use of the bus.
GNT#
Grant. This signal indicates that control of the PCI Bus has been granted and AudioPCI
97 is now the bus master.
INTA#
AudioPCI 97 supplies interrupt support for all possible interrupt configurations. This is
done so that the greatest possible flexibility can be achieved during the configuration
process.
PME#
Power Management Enable. This signal is not implemented in the ES1371. It is an output
only and will be set high. It should be left as a no connect on a PC board.
10.2. AC97 CODEC Interface
SDATAOUT
SYNC
SDATAIN
BCLK
Serial Data to AC97 CODEC
SYNC output to AC97 CODEC
Serial Data from AC97 CODEC
Bit Clock from AC97 CODEC
ENSONIQ Proprietary Information
ENSONIQ AudioPCI 97 Specification Rev 1.1 Oct 1, 1997
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