ES1371 Datasheet, PDF (2/37 Pages) List of Unclassifed Manufacturers – ENSONIQ AudioPCI 97 digital controller

ENSONIQ Proprietary Information
2. DESIGN CONCEPT
AudioPCI 97 is a PCI bus master and slave device that is best understood by looking at the device as four
interactive subsystems: the PCI interface, DMA control, LEGACY functions, and the CODEC.
2.1. PCI Interface
The PCI subsystem is a bus master interface that performs the memory accesses to keep the Audio cache
buffers full and empties the A/D Converter (or I2S input) buffer to main memory as required.
The fundamental concept of AudioPCI 97 is that the PCI interface controller has a sufficiently large internal
(on-chip) memory cache to meet the memory bandwidth requirements. There is a Sound Cache block of 64
bytes for each of the audio channels. It is the responsibility of the DMA control and the software to keep
the buffers full.
All system control registers are accessed via I/O on the PCI bus. AudioPCI 97 uses 16 Long Words in the
I/O space for control registers. All registers are read as Long Words. All registers are written in byte word
or longword format.
2.2. DMA Control
AudioPCI 97 essentially implements a 3 channel DMA controller. These virtual DMA channels are
implemented via the CCB, PCI and Serial interface modules. The Serial interface signals the CCB module
when a cache transfer is required (playback or record). The CCB module then signals the PCI module to
initiate a bus master data transfer. At this point the CCB and PCI modules will control the data transfer
between host system memory and the AudioPCI 97 internal cache.
2.3. LEGACY
The LEGACY subsystem is the circuitry required to perform SoundBlaster, OPL-FM and MPU-401
emulation. Functionally AudioPCI 97 traps on access of the SoundBlaster registers and then issues the
appropriate IRQ or SERR command on the PCI bus. AudioPCI 97 handles the Legacy DMA function in a
similar fashion. The exact functionality of the block cannot be fully disclosed at this time due to pending
patent protection for the application of this technique.
2.4. CODEC
The Codec controller supports any AC97 compliant CODEC. The functionality of the A/D and D/A
sections are similar to those found in other standard CODECs. The A/D portion of the Codec is handled as
an independent asynchronous event with a DMA buffer control structure. Each time the A/D FIFO is filled,
a Bus Master request occurs and the FIFO is transferred to main memory.
ENSONIQ Proprietary Information
ENSONIQ AudioPCI 97 Specification Rev 1.1 Oct 1, 1997
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