ES1371 Datasheet, PDF (30/37 Pages) List of Unclassifed Manufacturers – ENSONIQ AudioPCI 97 digital controller

ENSONIQ Proprietary Information
9. PCI BUS Description and Signals
AudioPCI 97 is designed to adhere to the PCI Local Bus Specification Revision 2.2, as such it complies
with all requirements for bus master capability. It is a 32 bit device and does not currently support the
optional 64 bit bus modes. Of the optional pins described in the PCI specification, AudioPCI 97 only uses
Interrupts.
Although the Sample buffer space is referred to as cache, it is not the system memory cache described in the
PCI specification. This cache is a local sound memory cache and is not part of the directly accessible
system memory. Note: The “#” symbol indicates a low active signal.
9.1. Parity
AudioPCI 97 implements the PAR signal. This signal is an even parity check described in the PCI
specification. AudioPCI 97 will generate PAR whenever it drives AD[31:0]. Although AudioPCI will
generate PAR , it will not generate the Bus Error condition signals PERR# and SERR# due to parity errors
on data received. This exception is allowed in the PCI Specification section 3.8.2.
9.2. LOCK#
AudioPCI 97 does not support PCI bus lock functions.
9.3. Bus Speed
Since AudioPCI 97 uses a high speed intermediate buffer to transfer data to and from the PCI bus, it runs at
the standard 33 MHz. Rate. However, it is believed that the memory speed on the PCI bus may limit the
transaction rate by inserting one wait state. All latency calculations are based on this assumption.
ENSONIQ Proprietary Information
ENSONIQ AudioPCI 97 Specification Rev 1.1 Oct 1, 1997
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