LM3S317 Datasheet, PDF (317/379 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S317 Data Sheet
Register 6: Analog Comparator Control 0 (ACCTL0), offset 0x24
This register configures that comparator’s input and output.
Analog Comparator Control 0 (ACCTL0)
Offset 0x024
31
30
29
28
27
26
25
24
23
22
21
20
19
18
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Type
RO
Reset
0
reserved
RO
RO
0
0
TOEN
ASRCP
reserved TSLVAL
TSEN
ISLVAL
ISEN
RO
R/W
RR/OW
RR/OW
RO
RR/OW
RR/OW
RR/OW
RR/OW
RR/OW
RR/OW
0
0
0
0
0
0
0
0
0
0
0
17
16
RO
RO
0
0
1
0
CINV
RR/OW
0
reserved
RROO
0
Bit/Field
31:12
11
Name
reserved
TOEN
10:9
ASRCP
8
reserved
7
TSLVAL
6:5
TSEN
Type
RO
R/W
R/W
RO
R/W
R/W
Reset
0
0
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
The TOEN bit enables the ADC event transmission to the
ADC. If 0, the event is suppressed and not sent to the ADC. If
1, the event is transmitted to the ADC.
The ASRCP field specifies the source of input voltage to the
VIN+ terminal of the comparator. The encodings for this field
are as follows:
ASRCP Function
00
Pin value
01
Pin value of C0+
10
Internal voltage reference
11
Reserved
0
Reserved bits return an indeterminate value, and should
never be changed.
0
The TSLVAL bit specifies the sense value of the input that
generates an ADC event if in Level Sense mode. If 0, an ADC
event is generated if the comparator output is Low. Otherwise,
an ADC event is generated if the comparator output is High.
0
The TSEN field specifies the sense of the comparator output
that generates an ADC event. The sense conditioning is as
follows:
TSEN
00
01
10
11
Function
Level sense, see TSLVAL
Falling edge
Rising edge
Either edge
May 4, 2007
317
Preliminary