LM3S317 Datasheet, PDF (103/379 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S317 Data Sheet
Register 1: Flash Memory Protection Read Enable (FMPRE), offset 0x130
Note: Offset is relative to System Control base address of 0x400FE000
This register stores the read-only (FMPRE) protection bits for each 2-KB flash block and bits to
disable debug access through JTAG and SWD. This register is loaded during the power-on reset
sequence.
The factory setting for the FMPRE register is a value of 1 for all implemented flash banks and 0x2
for the DBG field. These bits implement a policy of open access, programmability, and debug
access. The register bits may be changed by writing the specific register bit. However, this register
is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a
1).
The changes are not permanent until the register is committed (saved), at which point the bit
change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by
executing a power-on reset sequence.
For additional information, see “Flash Memory Protection” on page 87.
Flash Memory Protection Read Enable (FMPRE)
Offset 0x130 and 0x134
31
30
29
28
27
26
25
DBG
Type R/W0
R/W0
RO
RO
RO
RO
RO
Reset
1
0
0
0
0
0
0
15
14
13
12
11
10
9
reserved
Type
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
24
23
22
21
20
19
18
17
16
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
Block7 Block6 Block5 Block4 Block3 Block2 Block1 Block0
RO
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
0
1
1
1
1
1
1
1
1
Bit/Field
31:30
Name
DBG
29:8
reserved
7:0
Block7-
Block0
Type
R/W0
RO
R/W0
Reset
0x2
0
0xFF
Description
Controls access to the debug access port (DAP)
through the JTAG and SWD interfaces. A value of
0x2 enables access. A value of 0 disables access.
Reserved bits return an indeterminate value, and
should never be changed.
Enable 2-KB flash blocks to be executed or read.
The policies may be combined as shown in Table
Table 7-1 on page 99.
May 4, 2007
103
Preliminary