LM3S317 Datasheet, PDF (252/379 Pages) List of Unclassifed Manufacturers – Microcontroller

Universal Asynchronous Receiver/Transmitter (UART)
Register 6: UART Line Control (UARTLCRH), offset 0x02C
The UARTLCRH register is the line control register. Serial parameters such as data length, parity
and stop bit selection are implemented in this register.
When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register
must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH
register.
UART Line Control (UARTLCRH)
Offset 0x02C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
SPS
WLEN
FEN STP2 EPS PEN BRK
Type
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:8
7
6:5
4
3
Name
reserved
SPS
WLEN
FEN
STP2
Type
RO
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
Description
Reserved bits return an indeterminate value, and should never
be changed.
UART Stick Parity Select
When bits 1, 2 and 7 of UARTLCRH are set, the parity bit is
transmitted and checked as a 0. When bits 1 and 7 are set and 2
is cleared, the parity bit is transmitted and checked as a 1.
When this bit is cleared, stick parity is disabled.
UART Word Length
The bits indicate the number of data bits transmitted or received
in a frame as follows:
0x3: 8 bits
0x2: 7 bits
0x1: 6 bits
0x0: 5 bits (default)
UART Enable FIFOs
If this bit is set to 1, transmit and receive FIFO buffers are
enabled (FIFO mode).
When cleared to 0, FIFOs are disabled (Character mode). The
FIFOs become 1-byte-deep holding registers.
UART Two Stop Bits Select
If this bit is set to 1, two stop bits are transmitted at the end of a
frame. The receive logic does not check for two stop bits being
received.
252
May 4, 2007
Preliminary