LM3S317 Datasheet, PDF (242/379 Pages) List of Unclassifed Manufacturers – Microcontroller

Universal Asynchronous Receiver/Transmitter (UART)
12.4
3. Write the fractional portion of the BRD to the UARTFBRD register.
4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of
0x00000060).
5. Enable the UART by setting the UARTEN bit in the UARTCTL register.
Register Map
Table 12-1 lists the UART registers. The offset listed is a hexadecimal increment to the register’s
address, relative to that UART’s base address:
„ UART0: 0x4000C000
Note: The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 254)
before any of the control registers are reprogrammed. When the UART is disabled during
a TX or RX operation, the current transaction is completed prior to the UART stopping.
Table 12-1. UART Register Map
Offset Name
Reset
Type Description
0x000
0x004
0x018
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x040
0x044
0xFD0
0xFD4
0xFD8
0xFDC
0xFE0
0xFE4
0xFE8
0xFEC
UARTDR
UARTRSR
UARTECR
UARTFR
UARTIBRD
UARTFBRD
UARTLCRH
UARTCTL
UARTIFLS
UARTIM
UARTRIS
UARTMIS
UARTICR
UARTPeriphID4
UARTPeriphID5
UARTPeriphID6
UARTPeriphID7
UARTPeriphID0
UARTPeriphID1
UARTPeriphID2
UARTPeriphID3
0x00000000
0x00000000
0x00000090
0x00000000
0x00000000
0x00000000
0x00000300
0x00000012
0x00000000
0x0000000F
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000011
0x00000000
0x00000018
0x00000001
R/W
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
W1C
RO
RO
RO
RO
RO
RO
RO
RO
Data
Receive Status (read)
Error Clear (write)
Flag Register (read only)
Integer Baud-Rate Divisor
Fractional Baud-Rate Divisor
Line Control Register, High byte
Control Register
Interrupt FIFO Level Select
Interrupt Mask
Raw Interrupt Status
Masked Interrupt Status
Interrupt Clear
Peripheral identification 4
Peripheral identification 5
Peripheral identification 6
Peripheral identification 7
Peripheral identification 0
Peripheral identification 1
Peripheral identification 2
Peripheral identification 3
See
page
244
246
248
250
251
252
254
255
256
258
259
260
261
262
263
264
265
266
267
268
242
May 4, 2007
Preliminary