M12S128168A_08 Datasheet, PDF (8/45 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
M12S128168A
SIMPLIFIED TRUTH TABLE
COMMAND
BA0
A11
CKEn-1
CKEn
CS RAS
CAS
WE
DQM
A10/AP
BA1
A9~A0
Note
Register
Mode Register set
H
Extended Mode Register
Set
H
X LL L L X
X LL L L X
OP CODE
1,2
OP CODE
1,2
Auto Refresh
H
3
H
LL L H X
X
Entry
L
3
Refresh
Self
Refresh
Exit
LH H H X
L
H
X
3
HX X X X
3
Bank Active & Row Addr.
H
X LL H H X V
Row Address
Read &
Auto Precharge Disable
H
Column Address Auto Precharge Enable
X LH L H X V
L
Column ₄
Address
H
(A0~A8) ^4,5
Write &
Auto Precharge Disable
H
Column Address Auto Precharge Enable
X LH L L X V
L ^Column 4
Address
H _(A0~A8) 4,5
Burst Stop
H
X LH H L X
X
6
Precharge
Bank Selection
All Banks
V
L
H
X LL H L X
X
X
H
Clock Suspend or
Active Power Down
HX X X
Entry
H
L
X
LV V V
X
Exit
L
H XX X X X
HX X X
Entry
H
L
X
LH H H
Precharge Power Down Mode
X
HX X X
Exit
L
H
X
LV V V
DQM
H
X
V
X
7
No Operating Command
H
X HX X X X
X
Entry
H
L
LH H L
X
Deep Power Down Mode
Exit
L
H XX X X X
X
Note :
(V = Valid , X = Don’t Care. H = Logic High , L = Logic Low )
1.OP Code : Operating Code
A0~A11 & BA0~BA1 : Program keys. (@ MRS)
2.MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3.Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge of command is meant by “Auto”.
Auto/self refresh can be issued only at all banks idle state.
4.BA0~BA1 : Bank select addresses.
If BA0 and BA1 are “Low” at read ,write , row active and precharge ,bank A is selected.
If BA0 is “Low” and BA1 is “High” at read ,write , row active and precharge ,bank B is selected.
If BA0 is “High” and BA1 is “Low” at read ,write , row active and precharge ,bank C is selected.
If BA0 and BA1 are “High” at read ,write , row active and precharge ,bank D is selected
If A10/AP is “High” at row precharge , BA0 and BA1 is ignored and all banks are selected.
5.During burst read or write with auto precharge. new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6.Burst stop command is valid at every burst length.
7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (write DQM latency is 0), but
makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2008
Revision: 1.1
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