M12S128168A_08 Datasheet, PDF (33/45 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
Page Read Cycle at Different Bank @ Burst Length = 4
M12S128168A
Note: 1. CS can be don’t cared when RAS , CAS and WE are high at the clock high going edge.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2008
Revision: 1.1
33/45