M12S128168A_08 Datasheet, PDF (2/45 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
SDRAM
FEATURES
y JEDEC standard 2.5V power supply
y LVTTL compatible with multiplexed address
y Four banks operation
y MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length ( 1, 2, 4, 8 & full page )
- Burst Type ( Sequential & Interleave )
y All inputs are sampled at the positive going edge of the
system clock
y Burst Read single write operation
y DQM for masking
y Auto & self refresh
y 64ms refresh period (4K cycle)
M12S128168A
2M x 16 Bit x 4 Banks
Synchronous DRAM
ORDERING INFORMATION
PRODUCT NO.
M12S128168A-6TG
M12S128168A-7TG
M12S128168A-10TG
M12S128168A-6BG
M12S128168A-7BG
M12S128168A-10BG
MAX
FREQ.
166MHz
143MHz
100MHz
166MHz
143MHz
100MHz
PACKAGE COMMENTS
TSOP II
TSOP II
TSOP II
BGA
BGA
BGA
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
GENERAL DESCRIPTION
The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.
Pin Arrangement
VDD 1
DQ0 2
VDDQ 3
DQ1 4
DQ2 5
VSSQ 6
DQ3 7
DQ4 8
VDDQ 9
DQ5 10
DQ6 11
VSSQ 12
DQ7 13
VDD 14
LDQM 15
WE 16
CAS 17
RAS 18
CS 19
BA0 20
BA1 21
A10/AP ₂₂
A0 ₂₃
A1 ₂₄
A2 ₂₅
A3 ₂₆
VDD ₂₇
54 VSS
53 DQ15
52 VSSQ
51 DQ14
50 DQ13
49 VDDQ
48 DQ12
47 DQ11
46 VSSQ
45 DQ10
44 DQ9
43 VDDQ
42 DQ8
41 VSS
40 NC
39 UDQM
38 CLK
37 CKE
36 NC
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 VSS
Elite Semiconductor Memory Technology Inc.
1
2
3
4
5
6
7
8
9
A
VSS DQ15 VSSQ
VDDQ DQ0 VDD
B
DQ14 DQ13 VDDQ
C
DQ12 DQ11 VSSQ
VSSQ DQ2 DQ1
VDDQ DQ4 _DQ3
D
DQ10 DQ9 VDDQ
VSSQ DQ6 DQ5
E
DQ8
NC
VSS
VDD LDQM DQ7
F
UDQM CLK CKE
G
NC
A11
A9
CAS RAS
WE
BA0 BA1
CS
H
A8
A7
A6
J
VSS
A5
A4
A0
A1
A10
A3
A2
VDD
Publication Date: Apr. 2008
Revision: 1.1
2/45