M12S128168A_08 Datasheet, PDF (6/45 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
M12S128168A
AC OPERATING TEST CONDITIONS (V_DD = 2.5V ± 0.2V，T_A = 0 to 70 °C )
Parameter
Value
Unit
Input levels (Vih/Vil)
0.9xV_DDQ/0.2
V
Input timing measurement reference level
0.5xV_DDQ
V
Input rise and fall-time
tr/tf = 1/1
ns
Output timing measurement reference level
0.5xV_DDQ
V
Output load condition
See Fig. 2
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
-6
Row active to row active delay
t_RRD(min)
12
RAS to CAS delay
t_RCD(min)
18
Row precharge time
t_RP(min)
18
Row active time
t_RAS(min)
40
t_RAS(max)
@ Operating
t_RC(min)
58
Row cycle time
@ Auto refresh t_RFC(min)
60
Last data in to col. address delay
t_CDL(min)
Last data in to row precharge
t_RDL(min)
Last data in to burst stop
t_BDL(min)
Refresh period (4,096 rows)
t_REF(max)
Version
-7
14
20
20
42
100
63
70
1
2
1
64
Unit
Note
-8
20
ns
1
30
ns
1
30
ns
1
60
ns
1
us
90
ns
1
100
ns
1,5
t_CK
2
t_CK
2
t_CK
2
ms
6
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2008
Revision: 1.1
6/45