M12S128168A_08 Datasheet, PDF (37/45 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
M12S128168A
Clock Suspension & DQM Operation Cycle @ CAS Letency = 2 , Burst Length = 4
*Note : 1. DQM is needed to prevent bus contention
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2008
Revision: 1.1
37/45