S1K70000 Datasheet, PDF (92/379 Pages) Epson Company – STANDARD CELL / EMBEDDED ARRAY

Chapter 4 Types of Input/Output Buffers and Their Use
4.5.5 Gated Cells
4.5.5.1 Overview
The dual-power-supply Gated cells are outlined in Section 4.2.5.1, “Overview.”
(The Gated cells for the dual-power-supply specification are LVDD cells).
4.5.5.2 Features
For the features of the dual-power-supply Gated cells, refer to Section 4.2.5.2, “Features.”
4.5.5.3 Usage Precautions
For the precautions to be taken in the use of dual-power-supply Gated cells, refer to
Section 4.2.5.3, “Usage Precautions.”
4.5.5.4 List of Cells
Table 4-70 Gated Cell Input Buffers List
Cell Name^{*1, *2}
Input Level
Whether Pull-up/Pull-down Resistors are
Included
LIBATX
LIBAP#TX
LIBAD#TX
LVCMOS
LVCMOS
LVCMOS
None
Pull-up resistor
Pull-down resistor
Notes
*1: The # denotes 1 or 2, with the pull-up/pull-down resistance values corresponding to Type 1 and
Type 2, respectively (for details, refer to Table 4-53).
*2: In addition to the configurations shown in Table 4-70, the Gated input buffers may be configured
without test pins.
Customers desiring to use such configurations should direct inquiries to Epson.
Table 4-71 Gated Cell Bi-directional Buffers List
Input Level
Function
LVCMOS
Bi-directional output for high speed
Bi-directional output for low noise
I_OH/I_OL
Type 1
Type 2
Type 3
Type 4
Type 1
Type 2
Type 3
Type 4
Cell Name^*1,*2
LBBA#ATX
LBBA#BTX
Notes
*1: The # denotes 1, 2, 3, or 4, with the IOH/IOL values corresponding to Type 1, Type 2, Type 3, and
Type 4, respectively (for details, refer to Table 4-59).
*2: In addition to the configurations shown in Table 4-71, the Gated bi-directional buffers may be
configured with pull-up/pull-down resistors or without test pins.
Customers desiring to use such configurations should direct inquiries to Epson.
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EPSON
STANDARD CELL S1K70000 SERIES
EMBEDDED ARRAY S1X70000 SERIES