S1K70000 Datasheet, PDF (328/379 Pages) Epson Company – STANDARD CELL / EMBEDDED ARRAY

Chapter 8 Circuit Design that Takes Testability into Account
8.3.1 Circuit Configuration When Output Buffers with a Test Circuit are
Used
Figure 8-1 shows the configuration of the test circuit “L1TCIR2” recommended by Epson.
Figure 8-3 shows DC and AC test circuits and a practical example of a test circuit for
2-word x 2-bit RAM (this memory configuration does not actually exist, however). Refer
to these circuits and (1) through (4) below when configuring a test circuit. If RAM or
functional cells are included in your circuit, also refer to Section 8.4, “RAM and ROM Test
Circuits,” and Section 8.6, “Function Cell Test Circuits.”
(1) Adding and selecting pins for testing
To configure pins for testing, add the three types of test pins specified below.
For these test pins, select appropriate cells or buffers available.
• Test enable pin:
• Test mode select input pin:
• Monitor output pin for AC testing:
1 pin.
4 pins.
1 pin.
Table 8-1 Test Pins Constraints
Test Pin Type
Test enable pin
Number of
Pins
1 pin.
Test mode select
input pin
4 pins.
Monitor output pin for
AC testing
Output and
input/output pins
1 pin.
—
Name of
Pins (ex.)
TSTEN
INP0–INP3
OUT3
—
Constraints, Notes, etc.
Dedicated input pin. Use ITST1 for the input buffer.
H: test mode; L: normal mode
Input pin shareable with the user functions, but
cannot be shared with bi-directional pins. Avoid
sharing this pin with other input pins that have a
critical path.
Input pin shareable with the user functions, but
cannot be shared with N channel open drain cells
Output buffer with test mode (Input/output pins
allowed)
• About DC testing
This test checks whether all input and output pins satisfy the designated
specifications for DC characteristics. If no test circuits are included, customers
will be requested to create test patterns to enable measurement of DC
characteristics, which may require a huge number of man-hours. Use of a test
circuit facilitates the creation of test patterns and therefore makes it easy to
measure DC characteristics.
• AC testing
This test involves measuring pin-to-pin delays (delays in input pins to output pins).
If the actual operating frequency cannot be inspected using an LSI tester, the
operating speed will be guaranteed by measuring the delay in a specific path. If
the Epson-recommended test circuit “L1TCR2” is used, variations between lots will
be evaluated by measuring the dedicated AC path using an AC-test monitor output
pin. Because the recommended test circuit “L1TCR2” does so by judging the
difference in measured values between the tested device’s delay and the bypass
delay, consistent delay measurement that is not dependent on the intra-chip
320
EPSON
STANDARD CELL S1K70000 SERIES
EMBEDDED ARRAY S1X70000 SERIES