S1K70000 Datasheet, PDF (204/379 Pages) Epson Company – STANDARD CELL / EMBEDDED ARRAY

Chapter 6 Estimating Various Characteristic Values
(2) Delay time of output cells
The following describes the procedure for calculating the approximate amount of
propagation delay time, using the circuits in Figure 6-4 as an example. The output
pin has a capacitance of 100 pF added external to the chip.
Table 6-8 lists various characteristic values of dual-power-supply output cells
excerpted from the cell library.
Output pin
IN
A
PAD
HOB3AY
CL=100pF
Figure 6-4 Example Circuit for Calculation of the External Cell Propagation Delay Time
Table 6-8 Delay Characteristics of Output Cells (Power Supply HV_DD = 3.3 V / LV_DD = 1.8 V)
Cell
Name
Input
Pin
Fan-in
[LU]
Output
Pin
Fan-out
[LU]
From
Delay Characteristics (Typ.)
To Parameter
T₀
[ps]
K
[ps/10pF]
HOB3AY A
10.0 PAD
—
t_pLH
A PAD
t_pHL
984
1071
296.3
332.6
The delay time in the output cell HOB3AY under Typ. conditions is calculated using
Equation 6-2, as shown below.
Here, the symbol “↑” denotes a rise, and the symbol “↓” denotes a fall. Here, these
refer to the rising and falling transitions at the PAD for the output pin.
T_pd (IN↑→PAD↑) = T₀ (↑) + K (↑) x 100 (pF) / 10
= 984 + 296.3 x 100 (pF) / 10
= 3947 [ps]
T_pd (IN↓→PAD↓) = T₀ (↓) + K (↓) x 100 (pF) / 10
= 1071 + 332.6 x 100 (pF) / 10
= 4397 [ps]
6.2.4 Setup and Hold Times of the Flip-Flop (FF)
If the configured circuit is to operate properly with the desired logic, the timing of the
signals applied to the sequential circuit of the FF or of an MSI built with FFs is important.
The setup and hold times of FFs are closely related to this signal timing. Any data that is
supplied after the setup time or that has changed state within the hold time cannot be
written into the FF circuit properly. Therefore, these setup and hold times must be taken
into consideration in the timing design.
196
EPSON
STANDARD CELL S1K70000 SERIES
EMBEDDED ARRAY S1X70000 SERIES