S1K70000 Datasheet, PDF (315/379 Pages) Epson Company – STANDARD CELL / EMBEDDED ARRAY

Chapter 7 Circuit Design
Type
1
2
3
4
Table 7-10 LV Output Cells, V_DD or LV_DD = 1.5 V ± 0.1 V
Load Capacitance
30 pF
50 pF
100 pF
150 pF
0.014
0.016
0.017
0.019
0.026
0.029
0.031
0.034
0.043
0.048
0.053
0.059
0.083
0.091
0.100
0.111
200 pF
0.019
0.034
0.059
0.111
Calculation example: Determine whether the magnitude of noise is sufficiently large to
cause malfunction due to the simultaneous operation of outputs under the following
voltage and pin-layout conditions.
• Power-supply voltage : 3.3 V/1.8 V
• Input interface
: LVTTL for HV cells
LVCMOS for LV cells
Pin No.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
Cells Used
V_SS
HV_DD
LV_DD
HV cells, Type 4
HV cells, Type 4
HV cells, Type 4
HV_DD
LV cells, Type 3
LV cells, Type 3
LV_DD
V_SS
Output Load
Capacitance (pF)
125
100
175
75
150
First, because Tables 7-6 and 7-9 are used, round the output load capacitances up to
the nearest whole value.
(4) 125 pF → 150 pF
(5) 100 pF → 100 pF
(6) 175 pF → 200 pF
(8) 75 pF → 100 pF
(9) 150 pF → 150 pF
STANDARD CELL S1K70000 SERIES
EMBEDDED ARRAY S1X70000 SERIES
EPSON
307