S1K70000 Datasheet, PDF (314/379 Pages) Epson Company – STANDARD CELL / EMBEDDED ARRAY

Chapter 7 Circuit Design
For dual-power-supply systems, make this determination separately for the HV output
cells in each closed loop between HVDD’s, LV output cells in each closed loop between
LVDD’s, and for all output cells in each closed loop between VSS’s.
Type
1
2
3
4
Table 7-6 HV Output Cells, HV_DD = 3.3 V ± 0.3 V
Load Capacitance
30 pF
50 pF
100 pF
150 pF
0.048
0.053
0.059
0.063
0.077
0.083
0.091
0.100
0.100
0.111
0.125
0.143
0.200
0.250
0.250
0.333
200 pF
0.063
0.100
0.143
0.333
Table 7-7 HV Output Cells, HV_DD = 3.3 V ± 0.3 V (When Using PCI)
Type
30 pF
50 pF
Load Capacitance
100 pF
150 pF
1
0.077
0.083
0.091
0.100
2
0.125
0.143
0.167
0.167
3
0.167
0.200
0.200
0.250
4
0.250
0.333
0.333
0.333
PCI
0.167
0.200
0.200
0.250
Note: This applies when a PCI3V cell exists in the closed loop.
200 pF
0.100
0.167
0.250
0.333
0.250
Type
1
2
3
4
Table 7-8 HV Output Cells, HV_DD = 2.5 V ± 0.2 V
Load Capacitance
30 pF
50 pF
100 pF
150 pF
0.056
0.063
0.067
0.077
0.077
0.083
0.091
0.100
0.167
0.200
0.200
0.250
0.250
0.333
0.333
0.333
200 pF
0.077
0.100
0.250
0.333
Type
1
2
3
4
Table 7-9 LV Output Cells, V_DD or LV_DD = 1.8 V ± 0.15 V
Load Capacitance
30 pF
50 pF
100 pF
150 pF
0.016
0.018
0.019
0.021
0.038
0.042
0.045
0.050
0.063
0.071
0.077
0.083
0.125
0.143
0.167
0.167
200 pF
0.021
0.050
0.083
0.167
306
EPSON
STANDARD CELL S1K70000 SERIES
EMBEDDED ARRAY S1X70000 SERIES