S1K70000 Datasheet, PDF (364/379 Pages) Epson Company – STANDARD CELL / EMBEDDED ARRAY

Chapter 8 Circuit Design that Takes Testability into Account
Scan Design Checksheet (2/2)
! Check items (Mark the applicable items with a check.)
# $ The scan-clock pins have been treated in accordance with the design rules
described in Section 8.7.3, paragraph b.
# $ Asynchronous set/reset signals of registers have been treated in accordance with
the design rules described in Section 8.7.3, paragraph c.
# Transparent latches (Select one of the following.)
$ Not used
$ Treated in accordance with Section 8.7.3, paragraph d
$ Not treated in accordance with Section 8.7.3, paragraph d.
A reduction in the fault-detection rate is acknowledged.
$ Other: ____________________________________________________________________
# Cells or circuits the use of which is inhibited as described in Section 8.7.3,
paragraph e, do not exist.
# Functional macros or RAM cells (Select one of the following.)
$ Not used
$ Treated in accordance with Section 8.7.3, paragraph f
$ Not treated in accordance with Section 8.7.3, paragraph f.
A reduction in the fault-detection rate is acknowledged.
$ Other: ____________________________________________________________________
# Internal 3-state bus (Select one of the following.)
$ Not used
$ Treated in accordance with Section 8.7.3, paragraph g
$ Not treated in accordance with Section 8.7.3, paragraph g.
A reduction in the fault-detection rate is acknowledged.
$ Other: ____________________________________________________________________
# External cells with various control pins (Select one of the following.)
$ Not used
$ Treated in accordance with Section 8.7.3, paragraph h
$ Not treated in accordance with Section 8.7.3, paragraph h.
A reduction in the fault-detection rate is acknowledged.
$ Other: ____________________________________________________________________
# Other
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356
EPSON
STANDARD CELL S1K70000 SERIES
EMBEDDED ARRAY S1X70000 SERIES