S1K70000 Datasheet, PDF (316/379 Pages) Epson Company – STANDARD CELL / EMBEDDED ARRAY

Chapter 7 Circuit Design
• Make determination for the closed loop between HV_DD’s ((2) to (7))
The HV output cells used in the closed loop between HVDD’s are (4), (5), and (6).
From the input interface and the power-supply voltage, make determination using the
coefficients given in Table 7-6.
∑ ^{mk = 0.333 + 0.250 + 0.333 = 0.916}
k
Thus, the result shows that the closed loop between HVDD’s satisfies the determination
criteria.
• Make determination for the closed loop between LV_DD’s ((3) to (10))
The LV output cells used in the closed loop between LVDD’s are (8) and (9).
From the input interface and the power-supply voltage, make determination using the
coefficients given in Table 7-9.
∑ ^{mk = 0.077 + 0.167 = 0.244}
k
Thus, the result shows that the closed loop between LVDD’s satisfies the determination
criteria.
• Make determination for the closed loop between V_SS’s ((1) to (11))
The output cells used in the closed loop between VSS’s are (4), (5), (6), (8), and (9).
From the input interface and the power-supply voltage, make determination using the
coefficients given in Table 7-6 for the HV output cells, and Table 7-9 for the LV output
cells.
∑ ^{mk = 0.333 + 0.250 + 0.333 + 0.077 + 0.167 = 1.160}
k
Thus, the result shows that the noise restraints for malfunction due to the
simultaneous operation of outputs are not met.
Therefore, change the pin layout by moving VSS at (11) to a position between (8) and (9)
so that the cells in the closed loop between VSS’s are (4), (5), (6), and (8).
Pin No.
Cells Used
Output Load
Capacitance (pF)
(1)
V_SS
(2)
HV_DD
(3)
LV_DD
(4)
HV cells, Type 4
125
(5)
HV cells, Type 4
100
(6)
HV cells, Type 4
175
(7)
HV_DD
(8)
LV cells, Type 3
75
(11)
V_SS
(9)
LV cells, Type 4
150
VSS moved to this point
(10)
LV_DD
Make determination for the closed loop between VSS’s in this pin layout.
308
EPSON
STANDARD CELL S1K70000 SERIES
EMBEDDED ARRAY S1X70000 SERIES